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Target Configuration Space
Table 7-21 · DMA Control Register 5C Hex (Continued)
Bit(s) Type
Description
DMA BAR Select
Used to select which of the backend memory BARs the DMA will address. These bits are used to drive the
DMA_BAR and BAR_SELECT outputs during the DMA transfer.
28:26
31:29
RW
RW
When set to '000', BAR 0 will be selected. When set to '110', the Expansion ROM will be selected. When set to
'111', a direct DMA access will be done. Data will be read from and written to the DMA data registers (54h), and no
backend cycle will be carried out. When direct DMA mode is used, the transfer count register (58h) must be
programmed to transfer one DWORD (0004 hex). The transfer width must be set to 32 bits.
Maximum Burst Length
When set to '000', the Master controller will attempt to complete the requested transfer in a single burst. When set to
a non-zero value, the Master will automatically break up long bursts and limit burst transfer lengths to 2 n –1 , where n is
the decimal value of bits 31:29. Therefore, maximum transfer lengths can be limited to 1, 2, 4, 8, 16, 32, or 64
dataphases. For example, if the maximum burst length is set to '101' (16 transfers), a 1,024-DWORD transfer count
would be broken up into 64 individual PCI accesses.
v4.0
115
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